Complementary Metal-Oxide-Semiconductor (CMOS) is the primary technology for ultra large-scale integrated (ULSI) circuits. These ULSI circuits combine two types of Metal-Oxide-Semiconductor (MOS) devices, namely P-channel Metal-Oxide-Semiconductor (PMOS) devices and N-channel Metal-Oxide-Semiconductor (NMOS) devices, on the same integrated circuit. To gain performance advantages, scaling down the size of MOS devices has been the principal focus of the microelectronics industry over the last two decades.
The conventional process of manufacturing MOS devices involves doping a silicon substrate and forming a gate oxide on the substrate followed by a deposition of polysilicon. A photolithographic process is used to etch the polysilicon to form the device gate.
As the demand for higher performance semiconductor devices continues, smaller gate length (critical dimension) is the remedy of choice. Because the desired gate length is smaller than the smallest gate length current lithography light sources can provide, alternative methods have been developed to reduce the gate length. One such technique is trimming the polysilicon gate photoresist mask to smaller dimensions using an anisotropic oxygen plasma process prior to when the gate etch begins. Subsequently, the polysilicon gates are formed using a conventional etching process. The polysilicon gates thus formed replicate the dimensions of the trimmed photoresist masks, resulting in smaller gate lengths. While this approach is still viable, there are several problems associated with the photoresist mask trimming technique, namely, increased cycle time and process complexity due to the additional oxygen plasma process and the required cleaning processes, resulting in an undesirable increase in cost and yield loss.
Another technique to provide smaller gate length is to trim the hard mask (also known as anti-reflective coating which is used for enhancing the imaging effect in photolithography processing) underneath the photoresist mask in addition to trimming the photoresist mask. This hard mask and photoresist mask trimming process has the same problems associated with it as the photoresist mask trimming process, namely increased cycle time and process complexity, and undesirable increase in cost and yield loss.
Another way that a smaller gate length can be formed is to over-expose the photoresist mask. One of the disadvantages associated with this technique is that it represents a significant increase in process complexity because the over-exposure process is very difficult to control. The increase in process complexity adversely increase cycle time, cost and yield loss.
One other technique to form smaller gate length is to use phase shift masks. The disadvantages associated with the phase shift mask method are complicated photolithography tool and process which often times result in increase cycle time, cost and yield loss.
As the device sizes are scaled down, the gate length, source junctions and drain junctions have to scale down. As the gate length reduces, the channel length between the source and drain is shortened. The shortening in channel length has led to several severe problems.
One of the problems associated with shortened channel length is the so-called "hot carrier effect". As the channel length is shortened, the maximum electric field E.sub.m becomes more isolated near the drain side of the channel causing a saturated condition that increases the maximum energy on the drain side of the MOS device. The high energy causes electrons in the channel region to become "hot". The electron generally becomes hot in the vicinity of the drain edge of the channel where the energy arises. Hot electrons can degrade device performance and cause breakdown of the device. Moreover, the hot electrons can overcome the potential energy barrier between the silicon substrate and the silicon dioxide layer overlying the substrate, which causes hot electrons to be injected into the gate oxide.
Problems arising from hot carrier injections into the gate oxide include generation of a gate current and generation of a positive trapped charge which can permanently increase the threshold voltage of the MOS device. These problems are manifested as an undesirable decrease in saturation current, decrease of the transconductance and a continual reduction in device performance caused by trapped charge accumulation. Thus, hot carrier effects cause unacceptable performance degradation in MOS devices built with conventional drain structures when channel lengths are short.
Reducing the maximum electric field E.sub.m in the drain side of the channel is a popular way to control the hot carrier injections. A common approach to reducing E.sub.m is to minimize the abruptness in voltage changes near the drain side of the channel. Minimizing abrupt voltage changes reduces E.sub.m strength and the harmful hot carrier effects resulting therefrom. Reducing E.sub.m occurs by replacing an abrupt drain doping profile with a more gradually varying doping profile. A more gradual doping profile distributes E.sub.m along a larger lateral distance so that the voltage drop is shared by the channel and the drain. Absent a gradual doping profile, an abrupt junction can exist where almost all of the voltage drop occurs across the channel. The smoother or more gradual the doping profile, the smaller E.sub.m is which results in lesser hot carrier injections.
To try to remedy the problems associated with hot carrier injections, alternative drain structures such as lightly doped drain (LDD) structures have been developed. LDD structures provide a doping gradient at the drain side of the channel that leads to the reduction in E.sub.m. The LDD structures act as parasitic resistors to absorb some of the energy into the drain and thus reduce maximum energy in the channel region. This reduction in energy reduces the formation of hot electrons. To further minimize the formation of hot electrons, an improvement in the gradual doping profile is needed.
In most typical LDD structures of MOS devices, sources/drains are formed by two implants with dopants. One implant is self-aligned to the polysilicon gates to form shallow source/drain extension junctions or the lightly doped source/drain regions. Oxide or oxynitride spacers are then formed around the polysilicon gate. With the shallow drain extension junctions protected by the spacers, a second implant with heavier dose is self-aligned to the oxide spacers around polysilicon gates to form deep source/drain junctions. There would then be a rapid thermal anneal (RTA) for the source/drain junctions to enhance the diffusion of the dopants implanted in the deep source/drain junctions so as to optimize the device performance. The purpose of the first implant is to form a LDD at the edge near the channel. In a LDD structure, almost the entire voltage drop occurs across the lightly doped drain region. The second implant with heavier dose forms low resistance deep drain junctions, which are coupled to the LDD structures. Since the second implant is spaced from the channel by the spacers, the resulting drain junction adjacent the light doped drain region can be made deeper without impacting device operation. The increased junction depth lowers the sheet resistance and the contact resistance of the drain.
One significant problem associated with the LDD structures is the formation of parasitic capacitors. These parasitic capacitors are formed due to the diffusion of dopants from the LDD towards the channel regions underneath the polysilicon gates as a result of RTA and other heating processes in the manufacturing of the transistors. These parasitic capacitors are highly undesirable because they slow down the switching speed of the transistors. The adverse speed impact increases disproportionately with shortened channels. Basically, the parasitic capacitance due to LDD structures as a percentage of the total transistor capacitance is higher for sub-0.18 micron transistors than it is for a 0.18 micron transistor and even worse for a sub-0.13 transistor, making the adverse speed impact much more significant in smaller transistors.
The conventional approaches to reduce parasitic capacitance have been to reduce LDD implant dosage or scaling down the operating voltage. However, these approaches also degrade the performance of the transistors.
Methods to reduce gate length in MOS transistors without the problems associated with the prior art techniques, to minimize the formation of hot carriers by improving the gradual doping profile in LDD structures, and to reduce the parasitic capacitance due to LDD structures without compromising transistor performance have long been sought but have eluded those skilled in the art.